AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 212

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

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AMD-K6™-IIIE+ Embedded Processor Data Sheet
7.6
Table 33. Encodings for Special Bus Cycles
Notes:
1. A[31:5] = 0
2. Supported on the low-power versions only.
Basic Special Bus
Cycle
190
BE[7:0]#
FDh
FBh
BFh
EFh
F7h
FBh
FEh
A[4:3]
00b
00b
00b
00b
00b
00b
10b
Special Bus Cycles
1
Special Bus Cycle
Stop Grant
EPM Stop Grant
Flush Acknowledge
Writeback
Halt
Flush
Shutdown
The AMD-K6-IIIE+ processor drives special bus cycles that
include the following:
During all special cycles, D/C# = 0, M/IO# = 0, and W/R# = 1.
BE[7:0]# and A[31:3] are driven to differentiate among the
special cycles, as shown in Table 33.
Note that the system logic must return BRDY# in response to all
processor special cycles.
Figure 77 on page 191 shows a basic special bus cycle.
The processor drives D/C# = 0, M/IO# = 0, and W/R# = 1 off the
same clock edge that it asserts ADS#.
In this example, BE[7:0]# = FBh and A[31:3] = 0000_0000h,
which indicates that the special cycle is a halt special cycle (See
Stop grant
Enhanced power management
Flush acknowledge
Cache writeback invalidation
Halt
Cache invalidation
Shutdown
2
Preliminary Information
WBINVD instruction
HLT instruction
Cause
STPCLK# sampled asserted
A dword access is made to the EPM 16-byte I/O block and the GSBC bit of the
EPMR register is set to 1
FLUSH# sampled asserted
INVD,WBINVD instruction
Triple fault
Bus Cycles
23543A/0—September 2000
Chapter 7