AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 305

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
14.5
Enter EPM Stop Grant
State
Exit EPM Stop Grant
State
Chapter 14
EPM Stop Grant State
This state is supported on the low-power versions of the
AMD-K6-IIIE+ processor. After receiving a write of a non-zero
value to the SGTC (Stop Grant Time-out Counter) field located
within the EPM 16-byte I/O block, the processor flushes its
instruction pipelines, completes all pending and in-progress
bus cycles, and performs the following:
The EPM Stop Grant state is like the Halt state in that the
processor disables most of its internal clock distribution in the
EPM Stop Grant state. In order to support the following
operations, the internal PLL still runs, and some internal
resources are still clocked in the EPM Stop Grant state.
Unlike the Halt and Stop Grant states, system-initiated inquire
cycles are not supported and must be prevented during the
EPM Stop Grant state.
FLUSH# is not recognized in the EPM Stop Grant state (unlike
while in the Halt state).
Upon entering the EPM Stop Grant state, all signals driven by
the processor retain their state as they existed following the
completion of the EPM Stop Grant special cycle.
The processor remains in the EPM Stop Grant state until the
allotted time expires, as determined by the value written to the
SGTC field, or until RESET is sampled asserted. Once the
allotted time expires, the processor returns to the Normal state.
After the transition to the Normal state, the processor resumes
execution at the instruction boundary on which the EPM Stop
Grant state was entered.
Drives the processor VID[4:0] output pins to the value stored
in the VIDO field of the EPM 16-byte I/O block (see “EPM
16-Byte I/O Block” on page 146) if the VIDC bit is set to 1.
Forwards the processor-to-bus clock ratio stored in the
IBF[2:0] field of the EPM 16-byte I/O block to the internal
PLL if the BDC[1:0] value is set to 1xb.
Time Stamp Counter (TSC): The TSC continues to count in
the EPM Stop Grant state.
Signal Sampling: The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
Clock Control
AMD-K6™-IIIE+ Embedded Processor Data Sheet
283