AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 227

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
9
Chapter 9
Cache Organization
The following sections describe the basic architecture and
resources of the AMD-K6-IIIE+ processor internal caches.
The performance of the AMD-K6-IIIE+ processor is enhanced
by writeback level-one (L1) and level-two (L2) caches.
The cache line size is 32 bytes, and lines are fetched from
external memory using an efficient pipelined burst transaction.
As the L1 instruction cache is filled from the L2 cache or from
external memory, each instruction byte is analyzed for
instruction boundaries using predecode logic. Predecoding
annotates each instruction byte in the L1 instruction cache with
information that later enables the decoders to efficiently
decode multiple instructions simultaneously.
Translation lookaside buffers (TLB) are used in conjunction
with the L1 cache to translate linear addresses to physical
addresses. The L1 instruction cache is associated with a
64-entry TLB, while the L1 data cache is associated with a
128-entry TLB.
The L1 cache is organized as separate 32-Kbyte instruction
and data caches, each with two-way set associativity.
The L2 cache is 256 Kbytes, and is organized as a unified,
four-way set-associative cache (See Figure 82 on page 206).
Cache Organization
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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