AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 133

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
5.22
Pin Attribute
Summary
Driven
Chapter 5
FERR# (Floating-Point Error)
Output
The assertion of FERR # indicates the occurrence of an
unmasked floating-point exception resulting from the
execution of a floating-point instruction. This signal is provided
to allow the system logic to handle this exception in a manner
consistent with IBM-compatible PC/AT systems. See “Handling
Floating-Point Exceptions” on page 237 for a system logic
implementation that supports floating-point exceptions.
The state of the numeric error (NE) bit in CR0 does not affect
the FERR# signal.
The processor is designed so that FERR # does not glitch,
enabling the signal to be used as a clocking source for system
logic.
The processor asserts FERR # on the instruction boundary of
the next floating-point instruction, MMX instruction, 3DNow!
instruction, or WAIT instruction that occurs following the
f l o a t i ng -po i nt i ns t r u c t i o n t h a t c a u s e d t h e u n m a s ke d
floating-point exception—that is, FERR# is not asserted at the
time the exception occurs. The IGNNE# signal does not affect
the assertion of FERR#.
FERR# is negated during the following conditions:
FERR# is always driven except in the Three-State Test mode.
See “IGNNE# (Ignore Numeric Exception)” on page 116 for
more details on floating-point exceptions.
Following the successful execution of the floating-point
instructions FCLEX, FINIT, FSAVE, and FSTENV
Under certain circumstances, following the successful
execution of the floating-point
FLDENV, and FRSTOR, which load the floating-point status
word or the floating-point control word
Following the falling transition of RESET
Signal Descriptions
AMD-K6™-IIIE+ Embedded Processor Data Sheet
instructions FLDCW,
111