AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 273

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
13
13.1
Chapter 13
Test and Debug
Built-In Self-Test (BIST)
The AMD-K6-IIIE+ processor implements various test and
debug modes to enable the functional and manufacturing
testing of systems and boards that use the processor. In
addition, the debug features of the processor allow designers to
debug the instruction execution of software components. This
chapter describes the following test and debug features:
Following the falling transition of RESET, the processor
unconditionally runs its built-in self test (BIST). The internal
resources tested during BIST include the following:
Built-In Self-Test (BIST)—The BIST, which is invoked after
the falling transition of RESET, runs internal tests that
exercise most on-chip RAM structures.
Three-State Test Mode—A test mode that causes the
processor to float its output and bidirectional pins.
Boundary-Scan Test Access Port (TAP) —The Joint Test
Action Group (JTAG) test access function defined by the
IEEE
Architecture (IEEE 1149.1-1990) specification.
Cache Inhibit—A feature that disables the processor’s
internal L1 and L2 caches.
Level-2 Cache Array Access Register (L2AAR)—The
AMD-K6-IIIE+ processor provides the L2AAR that allows for
direct access to the L2 cache and L2 tag arrays.
Debug Support—Consists of all x86-compatible software
debug features, including the debug extensions.
L1 instruction and data caches
L2 cache
Instruction and Data Translation Lookaside Buffers (TLBs)
Standard
Test and Debug
Test
AMD-K6™-IIIE+ Embedded Processor Data Sheet
Access
Port
and
Boundary-Scan
251