AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 236

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
9.7
214
Cache-Line Replacements
Cache-line fills initiate 32-byte burst read cycles from memory
on the system bus for the L1 instruction cache and the L1 data
cache. All L1 cache-line fills supplied from the system bus are
also filled in the L2 cache.
As programs execute and task switches occur, some cache lines
eventually require replacement.
When a cache miss occurs in the L1 cache, the required cache
line is filled from either the L2 cache, if the cache line is
present (L2 cache hit), or from external memory, if the cache
line is not present (L2 cache miss). If the cache line is filled
from external memory, the cache line is filled in both the L1
and the L2 caches.
Two forms of cache misses and associated cache fills can take
place—a tag-miss cache fill and a tag-hit cache fill.
If a L1 data-cache line being filled replaces a modified line, the
modified line is written back to the L2 cache if the cache line is
present (L2 cache hit). By design, if a cache line is in the
modified state in the L1 cache, this cache line can only exist in
the L2 cache in the exclusive state. During the writeback, the
L2 cache-line state is changed from exclusive to modified, and
the writeback does not occur on the system bus. If the
replacement writeback does not hit the L2 cache (L2 cache
miss), then the modified L1 cache line is written back on the
system bus, and the L2 cache is not updated. If the other cache
line in this sector is in the modified state, it is also written back
in the same manner.
In the case of a tag-miss cache fill, the level-one cache miss is
due to a tag mismatch, in which case the required cache line
is filled either from the level-two cache or from external
memory, and the level-one cache line within the sector that
was not required is marked as invalid.
In the case of a tag-hit cache fill, the address matches the
tag, but the requested cache line is marked as invalid. The
required level-one cache line is filled from the level-two
cache or from external memory, and the level-one cache line
within the sector that is not required remains in the same
cache state.
Preliminary Information
Cache Organization
23543A/0—September 2000
Chapter 9