AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 137

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
5.27
Pin Attribute
Summary
Sampled
Chapter 5
HOLD (Bus Hold Request)
Input
The system logic can assert HOLD to gain control of the
processor’s bus. When HOLD is sampled asserted, the processor
completes the current bus cycles, floats the processor bus, and
asserts HLDA in an acknowledgment that these events have
been completed.
The processor samples HOLD on every clock edge. If a
processor cycle is in progress while HOLD is sampled asserted,
HLDA is asserted one clock edge after the last BRDY # of the
cycle is sampled asserted. If the bus is idle, HLDA is asserted
one clock edge after HOLD is sampled asserted. HOLD is
recognized while INIT and RESET are sampled asserted.
Signal Descriptions
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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