AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 175

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
7
7.1
Bus Clock (CLK)
Waveform
Definitions
Chapter 7
Bus Cycles
Timing Diagrams
The following sections describe and illustrate the timing and
relationship of bus signals during various types of bus cycles. A
representative set of bus cycles is illustrated.
The timing diagrams illustrate the signals on the external local
bus as a function of time, as measured by the bus clock (CLK).
Throughout this chapter, the term clock refers to a single
bus-clock cycle. A clock extends from one rising CLK edge to
the next rising CLK edge. The processor samples and drives
most signals relative to the rising edge of CLK. The exceptions
to this rule include the following:
For each signal in the timing diagrams, the High level
represents 1, the Low level represents 0, and the Middle level
represents the floating (high-impedance) state.
When both the High and Low levels are shown, the meaning
depends on the signal:
Figure 58 on page 154 defines the different waveform
representations.
BF[2:0]—Sampled on the falling edge of RESET
FLUSH#—Sampled on the falling edge of RESET, also
sampled on the rising edge of CLK
All inputs and outputs are sampled relative to TCK in
Boundary-Scan Test Mode. Inputs are sampled on the rising
edge of TCK, outputs are driven off of the falling edge of
TCK.
A single signal indicates ‘don’t care’.
In the case of bus activity, if both High and Low levels are
shown, it indicates that the processor, alternate master, or
system logic is driving a value, but this value may or may not
be valid. (For example, the value on the address bus is valid
only during the assertion of ADS#, but addresses are also
driven on the bus at other times.)
Bus Cycles
AMD-K6™-IIIE+ Embedded Processor Data Sheet
153