AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 139

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Sampled
5.29
Pin Attribute
Summary
Sampled
Chapter 5
INIT (Initialization)
This signal is provided to allow the system logic to handle
exceptions in a manner consistent with IBM-compatible PC/AT
systems.
The processor samples IGNNE # as a level-sensitive input on
every clock edge. The system logic can drive the signal either
s y n c h ro n o u s ly o r a s y n c h ro n o u s ly. I f i t i s a s s e r t e d
asynchronously, it must be asserted for a minimum pulse width
of two clocks.
Input
The assertion of INIT causes the processor to empty its
pipelines, to initialize most of its internal state, and to branch
to address FFFF_FFF0h—the same instruction execution
starting point used after RESET. Unlike RESET, the processor
preserves the contents of its caches, the floating-point state, the
MMX state, Model-Specific Registers, the CD and NW bits of
the CR0 register, and other specific internal resources.
INIT can be used as an accelerator for 80286 code that requires
a reset to exit from Protected mode back to Real mode.
INIT is sampled and latched as a rising edge-sensitive signal.
INIT is sampled on every clock edge but is not recognized until
the next instruction boundary. During an I/O write cycle, it must
be sampled asserted a minimum of three clock edges before
BRDY # is sampled asserted if it is to be recognized on the
boundary between the I/O write instruction and the following
instruction.
If INIT is asserted synchronously (see Table 19 on page 140),
it can be asserted for a minimum of one clock.
If it is asserted asynchronously, it must have been negated
for a minimum of two clocks, followed by an assertion of a
minimum of two clocks.
Signal Descriptions
AMD-K6™-IIIE+ Embedded Processor Data Sheet
117