AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 42

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
20
they are designed to decode up to two x86 instructions per
clock.
Long Decoder. The commonly-used x86 instructions that are
greater than seven bytes but not more than 11 bytes long and
less-commonly-used x86 instructions that are up to seven bytes
long are handled by the long decoder. The long decoder only
performs one decode per clock and generates up to four RISC86
operations.
Vector Decoder. All other translations (complex instructions,
serializing conditions, interrupts and exceptions, etc.) are
handled by a combination of the vector decoder and RISC86
operation sequences fetched from an on-chip ROM. For
complex operations, the vector decoder logic provides the first
set of RISC86 operations and a vector (initial ROM address) to a
sequence of further RISC86 operations. The same types of
RISC86 operations are fetched from the ROM as those that are
generated by the hardware decoders.
Note: Although all three sets of decoders are simultaneously fed a
Grouped Operations. The decoders or the on-chip RISC86 ROM
always generate a group of four RISC86 operations. For decodes
that cannot fill the entire group with four RISC86 operations,
RISC86 NOP operations are placed in the empty locations of
the grouping. For example, a long-decoded x86 instruction that
converts to only three RISC86 operations is padded with a
single RISC86 NOP operation and then passed to the scheduler.
Up to six groups or 24 RISC86 operations can be placed in the
scheduler at a time.
Floating Point Instructions. All of the common, and a few of the
uncommon, floating-point instructions (also known as ESC
instructions) are hardware decoded as short decodes. This
decode generates a RISC86 floating-point operation and,
optionally, an associated floating-point load or store operation.
Floating-point or ESC instruction decode is only allowed in the
first short decoder, but non-ESC instructions can be decoded
simultaneously by the second short decoder along with an ESC
instruction decode in the first short decoder.
copy of the instruction buffer contents, only one of the three
types of decoders is used during any one decode clock.
Preliminary Information
Internal Architecture
23543A/0—September 2000
Chapter 2