AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 191

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Figure 66. Basic HOLD/HLDA Operation
Chapter 7
BE[7:0]#
A[31:3]
D[63:0]
BRDY#
M/IO#
HOLD
ADS#
HLDA
W/R#
D/C#
CLK
Figure 66 on page 169 shows a basic HOLD/HLDA operation. In
this example, the processor samples HOLD asserted during the
memory read cycle. It continues the current memory read cycle
until BRDY# is sampled asserted. The processor drives HLDA
and floats its outputs one clock edge after the last BRDY# of the
cycle is sampled asserted. The system logic can assert HOLD for
as long as it needs to utilize the bus. The processor samples
HOLD on every clock edge but does not assert HLDA until any
in-progress cycle or sequence of locked cycles is completed.
When the processor samples HOLD negated during a hold
acknowledge cycle, it negates HLDA off the next clock edge.
The processor regains control of the bus and can assert ADS#
off the same clock edge on which HLDA is negated.
Bus Cycles
AMD-K6™-IIIE+ Embedded Processor Data Sheet
169