AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 263

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
12
12.1
Chapter 12
System Management Mode (SMM)
SMM Operating Mode and Default Register Values
SMM is an alternate operating mode entered by way of a system
management interrupt (SMI#) and handled by an interrupt
service routine. SMM is designed for system control activities
s u ch a s p owe r m a n a g e m e n t . Th e s e a c t iv i t i e s a p p e a r
transparent to conventional operating systems like DOS and
Windows. SMM is targeted for use by the Basic Input Output
System (BIOS), specialized low-level device drivers, and the
operating system. The code and data for SMM are stored in the
SMM memory area, which is isolated from main memory.
The processor enters SMM by the assertion of the SMI#
interrupt and the processor’s acknowledgment by the assertion
of SMIACT#. At this point the processor saves its state into the
SMM memory state-save area and jumps to the SMM service
routine. The processor returns from SMM when it executes the
resume (RSM) instruction from within the SMM service
routine. Subsequently, the processor restores its state from the
SMM save area, negates SMIACT#, and resumes execution with
the instruction following the point where it entered SMM.
The following sections summarize the SMM state-save area,
entry into and exit from SMM, exceptions and interrupts in
SMM, memory allocation and addressing in SMM, and the SMI#
and SMIACT# signals.
The software environment within SMM has the following
characteristics:
Addressing and operation in real mode
4-Gbyte segment limits
Default 16-bit operand, address, and stack sizes, although
instruction prefixes can override these defaults
Control transfers that do not override the default operand
size truncate the EIP to 16 bits
Far jumps or calls cannot transfer control to a segment with
a base address requiring more than 20 bits, as in real mode
segment-base addressing
System Management Mode (SMM)
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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