AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 244
AMD-K6-IIIE+550ACR
Manufacturer Part Number
AMD-K6-IIIE+550ACR
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AMD-K6-IIIE550ACR.pdf
(370 pages)
Specifications of AMD-K6-IIIE+550ACR
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AMD-K6™-IIIE+ Embedded Processor Data Sheet
5. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state in the L1 data cache and in
6. Assumes the write allocate conditions as specified in “Write Allocate” on page 215 are not met.
7. Assumes the write allocate conditions as specified in “Write Allocate” on page 215 are met.
8. Assumes PWT is driven Low and WB/WT# is sampled High.
9. Assumes PWT is driven High or WB/WT# is sampled Low.
— Not applicable or none.
9.11
Inquire Cycles
222
the modified state in the L2 cache.
Cache Coherency
Different ways exist to maintain coherency between the system
memory and cache memories. Inquire cycles, internal snoops,
FLUSH#, WBINVD, INVD, and line replacements all prevent
inconsistencies between memories.
Inquire cycles are bus cycles initiated by system logic that
ensure coherency between the caches and main memory. In
systems with multiple bus masters, system logic maintains
cache coherency by driving inquire cycles to the processor.
System logic initiates inquire cycles by asserting AHOLD,
BOFF#, or HOLD to obtain control of the address bus and then
driving EADS#, INV (optional), and an inquire address
(A[31:5]).
This type of bus cycle causes the processor to compare the tags
for its L1 instruction and L1 data caches, and L2 cache, with the
inquire address.
Table 40 on page 225 lists valid combinations of MESI states
permitted for a cache line in the L1 and L2 caches, and shows
the effects of inquire cycles performed with INV equal to 0
(non-invalidating) and INV equal to 1 (invalidating).
If there is a hit to a shared or exclusive line in the L1 data
cache or the L2 cache, or a valid line in the L1 instruction
cache, the processor asserts HIT#.
If the compare hits a modified line in the L1 data cache or
the L2 cache, the processor asserts HIT# and HITM#. If
HITM# is asserted, the processor writes the modified line
back to memory.
If INV was sampled asserted with EADS#, a hit invalidates
the line.
If INV was sampled negated with EADS#, a hit leaves the
line in the shared state or transitions it from the exclusive or
modified state to the shared state.
Preliminary Information
Cache Organization
23543A/0—September 2000
Chapter 9
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