AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 182

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
Misaligned
Single-Transfer
Memory Read and
Write
160
Figure 61 on page 161 shows a misaligned (split) memory read
followed by a misaligned memory write. Any cycle that is not
aligned as defined in “SCYC (Split Cycle)” on page 129 is
considered misaligned. When the processor encounters a
misaligned access, it determines the appropriate pair of bus
cycles — each with its own ADS# and BRDY# — required to
complete the access.
The AMD-K6-IIIE+ processor performs misaligned memory
reads and memory writes using least-significant bytes (LSBs)
first followed by most-significant bytes (MSBs). Table 29 shows
the order. In the first memory read cycle in Figure 61, the
processor reads the least-significant bytes. Immediately after
the processor samples BRDY# asserted, it drives the second bus
cycle to read the most-significant bytes to complete the
misaligned transfer.
Table 29. Bus-Cycle Order During Misaligned Memory Transfers
Similarly, the misaligned memory write cycle in Figure 61
transfers the LSBs to the memory bus first. In the next cycle,
after the processor samples BRDY# asserted, the MSBs are
written to the memory bus.
Type of Access
Memory Write
Memory Read
Preliminary Information
Bus Cycles
First Cycle
LSBs
LSBs
Second Cycle
MSBs
MSBs
23543A/0—September 2000
Chapter 7