AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 262

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
11.3
Registers
Exceptions
FERR# and IGNNE#
240
Floating-Point and MMX™/3DNow!™ Instruction Compatibility
more information on 3DNow! instructions, see the 3DNow!™
Technology Manual, order# 21928. For more information on the
3DNow! technology DSP extensions, see the AMD Extensions to
the 3DNow!™ and MMX™ Instructions Sets Manual, order#
22466.
The multimedia execution unit can execute MMX instructions
in a single processor clock. All MMX and 3DNow! arithmetic
instructions are pipelined for higher performance. To increase
performance, the processor is designed to simultaneously
decode all MMX and 3DNow! instructions with most other
instructions.
The eight 64-bit MMX registers (which are also utilized by
3DNow! instructions) are mapped on the floating-point stack.
This enables backward compatibility with all existing software.
For example, the register saving event that is performed by
operating systems during task switching requires no changes to
the operating system. The same support provided in an
operating system’s interrupt 7 handler (Device Not Available)
for saving and restoring the floating-point registers also
supports saving and restoring the MMX registers.
There are no new exceptions defined for supporting the MMX
and 3DNow! instructions. All exceptions that occur while
decoding or executing an MMX or 3DNow! instruction are
handled in existing exception handlers without modification.
MMX instructions and 3DNow! instructions do not generate
f l o a t i n g -p o i n t e x c e p t i o n s . H oweve r, i f a n u n m a s ke d
floating-point exception is pending, the processor asserts
FERR# at the instruction boundary of the next floating-point
instruction, MMX instruction, 3DNow! instruction or WAIT
instruction.
The sampling of IGNNE# asserted only affects processor
o p e ra t i o n d u r i n g t h e ex e c u t i o n o f a n e r ro r -s e n s i t ive
f l oa t i n g -po i n t i n st r u c ti on , MMX i n st r u c t i on , 3D N ow !
instruction or WAIT instruction when the NE bit in CR0 is set
to 0.
Floating-Point and Multimedia Execution Units
Preliminary Information
23543A/0—September 2000
Chapter 11