AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 164

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

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AMD-K6™-IIIE+ Embedded Processor Data Sheet
5.57
Table 23. Bus Cycle Definition
Notes:
1. x means “don’t care”
Table 24. Special Cycles
Notes:
1. x means “don’t care”.
2. Supported on the low-power versions only.
142
Bus Cycle Initiated
Code Read, L1 Instruction Cache and L2 Cache Line Fill
Code Read, Noncacheable
Code Read, Noncacheable
Encoding for Special Cycle
Interrupt Acknowledge
I/O Read
I/O Write
Memory Read, L1 Data Cache and L2 Cache Line Fill
Memory Read, Noncacheable
Memory Read, Noncacheable
Memory Write, L1 Data Cache or L2 Cache Writeback
Memory Write, Noncacheable
Special Cycle
Stop Grant
Enhanced Power Management (EPM)
Stop Grant
Flush Acknowledge
(FLUSH# sampled asserted)
Writeback (WBINVD instruction)
Halt
Flush (INVD, WBINVD instruction)
Shutdown
2
Bus Cycle Definitions
Preliminary Information
1
0
0
0
0
0
0
Signal Descriptions
1
1
1
1
1
1
1
1
0
1
1
1
1
1
M/IO#
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
Generated by the CPU
1
1
0
1
1
1
1
D/C#
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
0
1
1
W/R#
0
0
0
1
0
0
1
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
CACHE#
0
1
1
1
1
1
1
0
x
0
1
0
0
0
0
0
0
0
x
23543A/0—September 2000
0
0
0
0
0
0
0
by System Logic
Generated
1
1
1
1
1
1
1
KEN#
Chapter 5
x
0
1
0
x
x
x
x
x
1
x
x
1
1
1
1
1
1
1
1
x
x
x
x
x
x
x
1