AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 249

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
9.12
9.13
Chapter 9
Writethrough and Writeback Coherency States
A20M# Masking of Cache Accesses
The terms writethrough and writeback apply to two related
concepts in a read-write cache like the AMD-K6-IIIE+ processor
L1 data cache and the L2 cache. The following conditions apply
to both the writethrough and writeback modes:
Although the processor samples A20M# as a level-sensitive
input on every clock edge, it should only be asserted in Real
mode. The processor applies the A20M# masking to its tags,
through which all programs access the caches. Therefore,
assertion of A20M# affects all addresses (cache and external
memory), including the following:
However, A20M# does not mask writebacks or invalidations
caused by the following actions:
Memory Writes—A relationship exists between external
memory writes and their concurrence with cache updates:
•
•
Coherency State—A relationship exists between MESI
coherency states and writethrough-writeback coherency
states of lines in the cache as follows:
•
•
Cache-line fills (caused by read misses or write allocates)
Cache writethroughs (caused by write misses or write hits to
lines in the shared state)
Internal snoops
Inquire cycles
The FLUSH# signal
An external memory write that occurs concurrently with
a cache update to the same location is a writethrough.
Writethroughs are driven as single cycles on the bus.
An external memory write that occurs after the processor
has modified a cache line is a writeback. Writebacks are
driven as burst cycles on the bus.
Shared and invalid MESI lines are in the writethrough
state.
Modified and exclusive MESI lines are in the writeback
state.
Cache Organization
AMD-K6™-IIIE+ Embedded Processor Data Sheet
227