AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 235

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
9.5
9.6
Chapter 9
L2 Cache Testing
Cache-Line Fills
The AMD-K6-IIIE+ processor provides the L2AAR MSR that
allows for direct access to the L2 cache and L2 tag arrays. For
more detailed information, refer to “L2 Cache and Tag Array
Testing” on page 264.
The processor performs a cache-line fill for any area of system
memory defined as cacheable. If an area of system memory is
not explicitly defined as uncacheable by the software or system
logic, or implicitly treated as uncacheable by the processor,
then the memory access is assumed to be cacheable.
Software can prevent caching of certain pages by setting the
PCD bit in the PDE or PTE. Additionally, software can define
regions of memory as uncacheable or write combinable by
programming the MTRRs in the UWCCR MSR (see “Memory
Type Range Registers” on page 231). Write-combinable
memory is defined as uncacheable.
The system logic also has control of the cacheability of bus
cycles. If it determines the address is not cacheable, system
logic negates the KEN# signal when asserting the first BRDY#
or NA# of a cycle.
The processor does not cache certain memory accesses such as
locked operations. In addition, the processor does not cache
PDE or PTE memory reads in the L1 cache (referred to as page
table walks). However, page table walks are cached in the L2
cache if the PDE or PTE is determined to be cacheable.
When the processor needs to read memory, the processor drives
a read cycle onto the bus. If the cycle is cacheable, the
processor asserts CACHE#. If the cycle is not cacheable, a
non-burst, single-transfer read takes place. The processor waits
for the system logic to return the data and assert a single
BRDY# (See Figure 60 on page 159). If the cycle is cacheable,
the processor executes a 32-byte burst read cycle. The processor
expects a total of four BRDY# signals for a burst read cycle to
take place (See Figure 62 on page 163).
Cache Organization
AMD-K6™-IIIE+ Embedded Processor Data Sheet
213