AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 303

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Exit Stop Grant State
Chapter 14
STPCLK# assertion by executing a Stop Grant special bus cycle.
After BRDY# is sampled asserted during this cycle, and then
EWBE# is also sampled asserted (if not masked off), the
processor enters the Stop Grant state.
The Stop Grant state is like the Halt state in that the processor
disables most of its internal clock distribution in the Stop Grant
state.
In order to support the following operations, the internal PLL
still runs, and some internal resources are still clocked in the
Stop Grant state:
FLUSH# is not recognized in the Stop Grant state (unlike while
in the Halt state).
Upon entering the Stop Grant state, all signals driven by the
processor retain their state as they existed following the
completion of the Stop Grant special cycle.
The AMD-K6-IIIE+ processor remains in the Stop Grant state
until it samples STPCLK# negated or RESET asserted. If
STPCLK# is sampled negated, the processor returns to the
Normal state in less than 10 bus clock (CLK) periods. After the
transition to the Normal state, the processor resumes execution
at the instruction boundary on which STPCLK# was initially
recognized.
If STPCLK# is recognized as negated in the Stop Grant state
and subsequently sampled asserted prior to returning to the
Normal state, the AMD-K6-IIIE+ processor guarantees that a
minimum of one instruction is executed prior to re-entering the
Stop Grant state.
If INIT, INTR (if interrupts are enabled), FLUSH#, NMI, or
SMI# are sampled asserted in the Stop Grant state, the
Inquire cycles—The processor transitions to the Stop Grant
Inquire state during an inquire cycle. After returning to the
Stop Grant state following the inquire cycle, the processor
does not execute another Stop Grant special cycle.
Time Stamp Counter (TSC)—The TSC continues to count in
the Stop Grant state.
Signal Sampling—The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
Clock Control
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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