AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 241

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Chapter 9
The following list describes the corresponding items in Figure
85:
1. CD Bit of CR0—When the cache disable (CD) bit within con-
2. PCD Signal—When the PCD (page cache disable) signal is
3. CI Bit of TR12—When the cache inhibit bit of Test Register
4. UC or WC—If a pending write cycle addresses a region of
5. Write to a Cacheable Page (CCR)—A write allocate is
6. Write to a Sector—A write allocate is performed if the
7. Less Than Limit (WAELIM)—The write allocate limit
8. Between 640 Kbytes and 1 Mbyte —Write allocate is not
trol register 0 (CR0) is set to 1, the cache fill mechanism for
both reads and writes is disabled and write allocate does
not occur.
driven High, caching for that page is disabled, even if KEN#
is sampled asserted, and write allocate does not occur.
12 is set to 1, L1 and L2 cache fills are disabled and write
allocate does not occur.
memory defined as write combinable or uncacheable by an
MTRR, write allocates are not performed in that region.
performed if the processor knows that a page is cacheable.
The CCR is used to store the page address of the last L1
cache fill for a read miss. See “Write to a Cacheable Page”
on page 216 for a detailed description of this condition.
address of a pending write cycle matches the tag address of
a valid L1 cache sector but the addressed cache line within
the sector is invalid. See “Write to a Sector” on page 216 for
a detailed description of this condition.
mechanism determines if the memory area being addressed
is less than the limit set in the WAELIM field of WHCR. If
the address is less than the limit, write allocate for that
memory address is performed as long as conditions 8
through 10 do not prevent write allocate (even if conditions
8 and 10 attempt to prevent write allocate, condition 5 or 6
allows write allocate to occur).
performed in the memory area between 640 Kbytes and 1
Mbyte. It is not considered safe to perform write allocations
between 640 Kbytes and 1 Mbyte (000A_0000h to
000F_FFFFh) because this area of memory is considered a
noncacheable region of memory (even if condition 8
attempts to prevent write allocate, condition 5 or 6 allows
write allocate to occur).
Cache Organization
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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