AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 151

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
5.42
Pin Attribute
Summary
Driven and Floated
Chapter 5
SCYC (Split Cycle)
Output
The processor asserts SCYC during misaligned, locked transfers
on the D[63:0] data bus. The processor generates additional bus
cycles to complete the transfer of misaligned data.
For purposes of bus cycles, the term aligned means:
SCYC is asserted off the same clock edge as ADS#, and negated
off the clock edge on which NA# or the last expected BRDY# of
the entire locked sequence is sampled asserted. SCYC is only
valid during locked memory cycles.
SCYC is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
Any 1-byte transfers
2-byte and 4-byte transfers that lie within 4-byte address
boundaries
8-byte transfers that lie within 8-byte address boundaries
Signal Descriptions
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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