EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 133
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Figure 2–63. Control Signal Selection per IOE
Altera Corporation
July 2005
Dedicated I/O
Clock [7..0]
I/O Interconnect
[15..0]
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
io_coe
io_cclr
io_cce_out
io_cce_in
io_cclk
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset,
clk_in, and clk_out.
selection.
In normal bidirectional operation, the input register can be used for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. The OE register can be used for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from local interconnect in the associated LAB,
dedicated I/O clocks, and the column and row interconnects.
shows the IOE in bidirectional configuration.
clk_in
clk_out
io_bclk[3..0]
Figure 2–63
ce_in
ce_out
io_bce[3..0]
illustrates the control signal
aclr/preset
Stratix Device Handbook, Volume 1
sclr/preset
io_bclr[3..0]
Stratix Architecture
oe
Figure 2–64
io_boe[3..0]
2–109
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