EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 675
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Altera Corporation
July 2005
Interface Implementation in Stratix & Stratix GX Devices
The 16-bit full-duplex LVDS implementation of the framer part of the
SFI-4 interface is shown in
synchronous interfacing and LVDS differential signaling up to 840 Mbps.
Stratix devices have embedded SERDES circuitry for serial and parallel
data conversion.
The source-synchronous I/O implemented in Stratix GX devices
optionally includes dynamic phase alignment (DPA). DPA automatically
and continuously tracks fluctuations caused by system variations and
self-adjusts to eliminate the phase skew between the multiplied clock and
the serial data, allowing for data rates of 1 Gbps. In non DPA mode the
I/O behaves similarly to that of the Stratix I/O. This document assumes
that DPA is disabled. However, it is simple to implement the same system
with DPA enabled to take advantage of its features. For more information
on DPA, see the Stratix GX Transceivers chapter in the Stratix GX Device
Handbook, Volume 1.
The fast PLL enables 622.08 Mbps data transmission by transmitting and
receiving a differential clock at rates of up to 645 MHz. The clocks
required in the SERDES for parallel and serial data conversion can be
configured from the received RXCLK (divided down), the TXCLK_SRC
(divided down), or the asynchronous core clock. See
Implementing SFI-4 in Stratix & Stratix GX Devices
Figure
9–4. Stratix devices support source-
Stratix Device Handbook, Volume 2
Figure
9–4.
9–5
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