EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 418
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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DDR Memory Support Overview
Figure 3–11. Extending the OE Disable by Half-a-Clock Cycle for a Write Transaction
Note to
(1)
3–22
Stratix Device Handbook, Volume 2
from System Clock)
−90° phase shifted
The waveform reflects the software simulation result. The OE signal is an active low on the device. However, the
Quartus II software implements this signal as an active high and automatically adds an inverter before the A
register D input.
(outclock for DQS)
(from logic array)
(from logic array)
(from logic array)
(from logic array)
(outclock for DQ,
Figure
System clock
OE for DQS
Write Clock
OE for DQ
datain_h
datain_l
DQS
3–11:
DQ
90˚
Figures 3–12
DQS signals.
and
by Half
a Clock
Delay
Cycle
3–13
summarize the IOE registers used for the DQ and
Preamble
D0
D1
D0
D1
D2
D2
D3
Note (1)
Altera Corporation
D3
Postamble
June 2006
OE
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