EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 643

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Revision History
Altera Corporation
Chapter
8
9
September 2004, v1.2
September 2004, v1.1
November 2003, v1.1
April 2003, v1.0
April 2003, v1.0
July 2005, v2.0
July 2005, v2.0
Date/Version
This section provides documentation on some of the IP functions offered
by Altera
of the Altera web site for a complete offering of IP cores for Stratix
devices.) The last chapter details design considerations for migrating
from the APEX
This section contains the following chapters:
■
■
■
The table below shows the revision history for
Chapter 8, Implementing 10-Gigabit Ethernet Using Stratix &
Stratix GX Devices
Chapter 9, Implementing SFI-4 in Stratix & Stratix GX Devices
Chapter 10, Transitioning APEX Designs to Stratix & Stratix GX
Devices
Updated Stratix GX device information.
●
●
●
●
●
●
●
●
®
for Stratix
Table 8–2 on page
Note 2.
Updated
Removed support for series and parallel on-chip termination.
No new changes in Stratix Device Handbook v2.0.
Updated Stratix GX device information.
Table 9–2 on page
Note 2.
Updated
No new changes in Stratix Device Handbook v2.0.
™
architecture.
Table 8–4 on page
Table 9–4 on page
®
devices. (Also see the Intellectual Property section
Section V. IP & Design
8–10: updated table, deleted Note 1, and updated
9–9: updated table, deleted Note 1, and updated
Changes Made
8–12.
9–10.
Considerations
Chapters 8
through 10.
Section V–1