EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 774

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Device Configuration Pins
11–56
Stratix Device Handbook, Volume 2
DATA[7..1]
DATA7
nWS
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device
Pin Name
I/O
I/O
I/O
User Mode
Parallel
configuration
schemes
(FPP and
PPA)
PPA
PPA
Configuration
Scheme
Inputs
Bidirectional In the PPA configuration scheme, the
Input
Pin Type
Data inputs. Byte-wide configuration data is
presented to the target device on
DATA[7..0]
these pins are dependent on the V
I/O banks that they reside in.
In serial configuration schemes, they function
as user I/Os during configuration, which means
they are tri-stated.
After PPA or FPP configuration,
are available as a user I/Os and the state of
these pin depends on the Dual-Purpose Pin
settings.
pin presents the
signal has been strobed low. The V
levels for this pin are dependent on the V
of the I/O bank that it resides in.
In serial configuration schemes, it functions as
a user I/O during configuration, which means it
is tri-stated.
After PPA configuration,
a user I/O and the state of this pin depends on
the Dual-Purpose Pin settings.
Write strobe input. A low-to-high transition
causes the device to latch a byte of data on the
DATA[7..0]
In non-PPA schemes, it functions as a user I/O
during configuration, which means it is tri-
stated.
After PPA configuration,
user I/O and the state of this pin depends on
the Dual-Purpose Pin settings.
. The V
pins.
RDYnBSY
Description
(Part 6 of 8)
I H
DATA7
and V
nWS
signal after the
Altera Corporation
is available as a
I L
DATA[7..1]
is available as
levels for
C C I O
I L
July 2005
and V
DATA7
of the
C C I O
nRS
I L