EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 653

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 8–7. Stratix & Stratix GX Device XSBI Receiver Implementation
Altera Corporation
July 2005
Stratix & Stratix GX PCS Receiver
Stratix & Stratix GX
Logic Array
f
Fast PLL
4 or 8
4 or 8
Stratix and Stratix GX devices contain up to eight fast PLLs. These PLLs
provide high-speed outputs for high-speed differential I/O support as
well as general- purpose clocking with multiplication and phase shifting.
The fast PLL incorporates this 180° phase shift. The Stratix and Stratix GX
device’s data realignment feature enables you to save more logic
elements (LEs). This feature provides a byte-alignment capability, which
is embedded inside the SERDES. The data realignment circuitry can
correct for bit misalignments by slipping data bits.
For more information about fast PLLs, see the Stratix Device Family Data
Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX
Device Family Data Sheet section of the Stratix GX Device Handbook,
Volume 1.
Stratix & Stratix GX SERDES
÷J
Register
Parallel
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
622 MHz
× W
Parallel-to-Serial
Register
W = 1
CH15
J = 4 or 8
CH0
Stratix Device Handbook, Volume 2
PMA_RXCLK_SRC
RX_D[15]
622 Mbps
622 MHz
RX_D[0]
Receiver
PMA
8–9