EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 519
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 519 of 864
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Figure 5–34. HyperTransport & LVPECL Differential Termination
Altera Corporation
July 2005
Transmitter
Differential
Figure 5–33. LVDS Differential On-Chip Termination
HyperTransport & LVPECL Differential Termination
HyperTransport and LVPECL I/O standards are terminated by an
external 100- resistor on the input pin.
with differential termination for the HyperTransport or LVPECL I/O
standard.
PCML Differential Termination
The PCML I/O technology is an alternative to the LVDS I/O technology,
and use an external voltage source (V
input side and a pair of 50- resistors on the output side.
shows the device with differential termination for PCML I/O standard.
LVDS Transmitter
Z
Z
0
0
= 50 Ω
= 50 Ω
High-Speed Differential I/O Interfaces in Stratix Devices
R
D
Z
Z
0
0
= 50 Ω
= 50 Ω
Differential Receiver
TT
Stratix Device Handbook, Volume 2
), a pair of 100- resistors on the
Figure 5–34
On-Chip 100-Ω Termination
R
LVDS Receiver with
D
shows the device
Figure 5–35
5–47
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