EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 767

IC STRATIX FPGA 10K LE 484-FBGA

EP1S10F484I6

Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheets

Specifications of EP1S10F484I6

Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S10F484I6
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
0
Part Number:
EP1S10F484I6
0
Part Number:
EP1S10F484I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S10F484I6N
Manufacturer:
XILINX
0
Part Number:
EP1S10F484I6N
Manufacturer:
ALTERA
0
Altera Corporation
July 2005
Jam Instructions
Each Jam statement begins with one of the instruction names listed in
Table
instructions, are reserved keywords that you cannot use as variable or
label identifiers in a Jam program.
Table 11–14
language. These keywords correspond to the state names specified in the
IEEE Std. 1149.1 JTAG specification.
Note to
(1)
BOOLEAN
CALL
CRC
DRSCAN
DRSTOP
EXIT
EXPORT
FOR
GOTO
IF
Test-Logic-Reset
Run-Test-Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR-Scan
Table 11–13. Instruction Names
Table 11–14. Reserved Keywords (Part 1 of 2)
IEEE Std. 1149.1 JTAG State Names
This instruction name is an optional language extension.
11–13. The instruction names, including the names of the optional
Table
shows the state names that are reserved keywords in the Jam
11–13:
INTEGER
IRSCAN
IRSTOP
LET
NEXT
NOTE
POP
POSTDR
POSTIR
PREDR
Configuring Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
RESET
IDLE
DRSELECT
DRCAPTURE
DRSHIFT
DREXIT1
DRPAUSE
DREXIT2
DRUPDATE
IRSELECT
Jam Reserved State Names
PREIR
PRINT
PUSH
RETURN
STATE
WAIT
VECTOR
VMAP
(1)
(1)
11–49

Related parts for EP1S10F484I6