EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 722
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Device Configuration Overview
11–4
Stratix Device Handbook, Volume 2
related I/O banks (3, 4, 7, and 8) where the following pins reside: TDI,
TMS, TCK, TRST, MSEL0, MSEL1, MSEL2, nCONFIG, nCE, DCLK, PLL_ENA,
CONF_DONE, nSTATUS. The VCCSEL pin can be pulled to 1.5, 1.8, 2.5, or
3.3-V for a logic high level. There is an internal 2.5-k pull-down resistor
on VCCSEL. Therefore, if you are using a pull-up resister to pull up this
signal, you need to use a 1-k resistor.
VCCSEL also sets the power-on-reset (POR) trip point for all the
configuration related I/O banks (3, 4, 7, and 8), ensuring that these I/O
banks have powered up to the appropriate voltage levels before
configuration begins. Upon power-up, the FPGA does not release
nSTATUS until V
banks are above their POR trip points. If you set VCCSEL to ground (logic
low), this sets the POR trip point for all configuration I/O banks to a
voltage consistent with 3.3-V/2.5-V signaling. When VCCSEL = 0, the
POR trip point for these I/O banks may be as high as 1.8 V. If V
of the configuration banks is set to 1.8 or 1.5 V, the voltage supplied to this
I/O bank(s) may never reach the POR trip point, which will not allow the
FPGA to begin configuration.
1
Table 11–3
V
input signaling voltages.
The VCCSEL signal does not control any of the dual-purpose pins,
including the dual-purpose configuration pins, such as the DATA[7..0]
and PPA pins (nWS, nRS, CS, nCS, and RDYnBSY). During configuration,
these dual-purpose pins drive out voltage levels corresponding to the
V
configuration, the dual-purpose pins inherit the I/O standards specified
in the design.
3.3-V/2.5-V
1.8-V/1.5-V
3.3-V/2.5-V
Table 11–3. VCCSEL Setting
CCIO
CCIO
V
CCIO
setting of the configuration I/O banks and your configuration
supply voltage that powers the I/O bank containing the pin. After
(banks 3,4,7,8)
If the V
configuration signals used require 3.3-V or 2.5-V signaling you
should set VCCSEL to V
trip point to enable successful configuration.
shows how you should set the VCCSEL depending on the
CCIO
CCINT
of I/O banks 3, 4, 7, or 8 is set to 1.5 or 1.8 V and the
and all of the V
3.3-V/2.5-V
3.3-V/2.5-V/1.8-V/1.5-V
1.8-V/1.5-V
Configuration Input
Signaling Voltage
CC
(logic high) in order to lower the POR
CCIO
s of the configuration I/O
GND
VCC
Not Supported
Altera Corporation
V
CCSEL
CCIO
July 2005
of any
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