EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 558

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Architecture
6–8
Stratix Device Handbook, Volume 2
Multiplier Stage
The multiplier stage supports 9
(The multiplier stage also support smaller multipliers. See
Modes” on page 6–18
block can perform many multiplications in parallel.
The multiplier operands can be signed or unsigned numbers. Two
signals, signa and signb, indicate the representation of the two
operands. For example, a logic 1 on the signa signal indicates that data
A is a signed number; a logic 0 indicates an unsigned number. The result
of the multiplication is signed if any one of the operands is a signed
number, as shown in
The signa and signb signals affect the entire DSP block. Therefore, all
of the data A inputs feeding the same DSP block must have the same sign
representation. Similarly, all of the data B inputs feeding the same DSP
block must have the same sign representation. The multiplier offers full
precision regardless of the sign representation.
1
Pipeline Registers
The output from the multiplier can feed a pipeline register or be
bypassed. You can use pipeline registers for any multiplier size;
pipelining is useful for increasing the DSP block performance,
particularly when using subsequent adder stages.
1
Table 6–3. Multiplier Signed Representation
Unsigned
Unsigned
Signed
Signed
By default, the Altera Quartus
perform unsigned multiplication when the signa and signb
signals are not used.
In the DSP block, pipelining improves the performance of
36
pipelining adds latency but does not improve performance.
Data A
36 multipliers. For 18
Table
for details.) Based on the data width, a single DSP
6–3.
Unsigned
Unsigned
Signed
Signed
Data B
9, 18
18 multipliers and smaller,
®
II software sets the multiplier to
18, or 36
36 multiplication.
Altera Corporation
Unsigned
Signed
Signed
Signed
Result
“Operational
July 2005