EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 317
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Figure 1–4. Enhanced PLL Signals
Notes to
(1)
(2)
(3)
Altera Corporation
July 2005
(1)
(2)
(2)
(2)
This input pin is shared by all enhanced and fast PLLs.
These are either single-ended or differential pins.
EP1S10, EP1S20, and EP1S25 devices in 672-pin ball grid array (BGA) and 484- and 672-pin FineLine BGA packages
only have two pairs of external clocks (i.e., pll_out0p, pll_out0n, pll_out1p, and pll_out1n).
Figure
1–4:
pllenable
inclk0
inclk1
areset
clkswitch
scanclk
scandata
scanaclr
clkena[5..0]
pfdena
extclkena[3..0]
Figure 1–4
shows all the possible ports of the enhanced PLLs.
active_clock
scandataout
clkbad[1..0]
pll_out0p
pll_out0n
pll_out1p
pll_out1n
pll_out2p
pll_out2n
pll_out3p
pll_out3n
clk[5..0]
extclk4
clkloss
locked
General-Purpose PLLs in Stratix & Stratix GX Devices
(3)
(3)
(3)
(3)
Stratix Device Handbook, Volume 2
Only PLLs
11 and 12
Only PLLs
5 and 6
Signal Driven by Internal Logic
Signal Driven to Internal Logic
Internal Clock Signal
Physical Pin
1–7
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