EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 438
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 438 of 864
- Download datasheet (11Mb)
Stratix & Stratix GX I/O Standards
4–10
Stratix Device Handbook, Volume 2
Figure 4–7. SSTL-3 Class I Termination
Figure 4–8. SSTL-3 Class II Termination
SSTL-2 Class I & II - EIA/JEDEC Standard JESD8-9A
The SSTL-2 I/O standard is a 2.5-V memory bus standard used for
applications such as high-speed DDR SDRAM interfaces. This standard
defines the input and output specifications for devices that operate in the
SSTL-2 logic switching range of 0.0 to 2.5 V. This standard improves
operation in conditions where a bus must be isolated from large stubs.
The SSTL-2 standard specifies an input voltage range of
– 0.3 V V
V
Figures 4–9
and output levels.
Figure 4–9. SSTL-2 Class I Termination
TT
to which the series and termination resistors are connected (see
I
Output Buffer
and 4–10). Stratix and Stratix GX devices support both input
Output Buffer
V
Output Buffer
CCIO
+ 0.3 V. SSTL-2 requires a 1.25-V V
25 Ω
25 Ω
25 Ω
V
TT
= 1.5 V
V
V
REF
REF
50 Ω
V
Z = 50 Ω
Z = 50 Ω
REF
= 1.25 V
Z = 50 Ω
= 1.5 V
= 1.5 V
V
V
TT
TT
V
TT
= 1.5 V
= 1.25 V
= 1.5 V
50 Ω
50 Ω
50 Ω
Input Buffer
Input Buffer
REF
Input Buffer
Altera Corporation
and a 1.25-V
June 2006
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