EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 694

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

TriMatrix Memory
10–10
Stratix Device Handbook, Volume 2
f
APEX 20K design contains flow-through memory, you must modify the
memory modules to target the Stratix and Stratix GX architectures (see
“Memory Megafunctions” on page 10–12
For more information about TriMatrix memory and converting flow-
through memory modules to pipelined, see the TriMatrix Embedded
Memory Blocks in Stratix & Stratix GX Devices chapter in the Stratix GX
Device Handbook and AN 210: Converting Memory from Asynchronous to
Synchronous for Stratix & Stratix GX Designs.
Same-Port Read-During-Write Mode
In same-port read-during-write mode, the RAM block can be in single-
port, simple dual-port, or true dual-port mode. One port from the RAM
block both reads and writes to the same address location using the same
clock. When APEX II or APEX 20K devices perform a same-port read-
during-write operation, the new data is available on the falling edge of
the clock cycle on which it was written, as shown in
Stratix and Stratix GX devices perform a same-port read-during-write
operation, the new data is available on the rising edge of the same clock
cycle on which it was written, as shown in
all TriMatrix memory blocks.
Figure 10–4. Falling Edge Feed-Through Behavior
(APEX II & APEX 20K Devices)
Note to
(1)
Figures 10–4
the outputs are not registered.
Figure
10–4:
and
data_out
data_in
inclock
10–5
wren
assume that the address stays constant throughout and that
Old
Note (1)
A
A
Figure
for more information).
10–5. This holds true for
B
Figure
Altera Corporation
10–4. When
July 2005