EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 565

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 6–8. DSP Block Row Interface
Altera Corporation
July 2005
Clocks
Row
LAB
Interconnect
30 Local
Signals
Unit Control
DSP Row
DSP Row
DSP Row
Block
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
The row interface block generates the control signals and routes them to
the DSP block. Each DSP block has 18 control signals:
■
■
■
■
■
■
The signa, signb, and addnsub[1..0], accum_sload[1..0]
signals have independent clocks and clears and can be registered
individually. When each 18
to two 9
signals.
generates the data and control signals.
21 Signals for
Data to Input
3
Register
Four clock signals (clock[3..0]), which are available to each bank
of DSP blocks
Four clear signals (aclr[3..0]), which are available to each bank
of DSP blocks
Four clock enable signals (ena[3..0]), which the whole DSP block
can use
signa and signb, which are specific to each DSP block
addnsub[1..0] signals
accum_sload[1..0] signals
Figure 6–8
9 multipliers, each 9
Detail of
1 DSP Row
shows the DSP block row interface and shows how it
18 multiplier in the DSP block splits in half
DSP Blocks in Stratix & Stratix GX Devices
Row Interface
DSP Row 1
DSP Row 2
DSP Row 3
DSP Row 4
DSP Row 5
DSP Row 6
DSP Row 7
DSP Row 8
9 multiplier has independent control
DSP Block
Stratix Device Handbook, Volume 2
Registers
Input
Block
DSP
6–15