EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 495
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Figure 5–16. Fast PLL & Channel Layout in EP1S10, EP1S20 & EP1S25 Devices
Notes to
(1)
(2)
(3)
Altera Corporation
July 2005
Wire-bond packages only support up to 624 Mbps until characterization shows otherwise.
See
There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of
its bank quadrant (e.g., if PLL 2 clocks PLL 1’s channel region), those clocked channels support up to 840 Mbps.
Transmitter Channels (2)
Transmitter Channels (2)
Up to 20 Receiver and
Up to 20 Receiver and
Tables 5–10
Figure
Transmitter
Transmitter
Receiver
Receiver
5–16:
CLKIN
CLKIN
f
through
5–14
Fast PLL SERDES Channel Support
The Quartus II MegaWizard Plug-In Manager only allows you to
implement up to 20 receiver or 20 transmitter channels for each fast PLL.
These channels operate at up to 840 Mbps. For more information on
implementing more than 20 channels, see
receiver and transmitter channels are interleaved such that each I/O bank
on the left and right side of the device has one receiver channel and one
transmitter channel per row.
layout in EP1S10, EP1S20, and EP1S25 devices.
PLL and channel layout in EP1S30 to EP1S80 devices.
For more the number of channels in each device, see
5–14.
PLL 1
PLL 2
for the exact number of channels each package and device density supports.
Fast
Fast
(3)
High-Speed Differential I/O Interfaces in Stratix Devices
(3)
Figure 5–16
PLL 4
PLL 3
Stratix Device Handbook, Volume 2
Fast
Fast
shows the fast PLL and channel
“Fast PLLs” on page
Figure 5–17
Note (1)
Up to 20 Receiver and
Transmitter Channels (2)
Up to 20 Receiver and
Transmitter Channels (2)
Transmitter
Receiver
CLKIN
CLKIN
Transmitter
Receiver
Tables 5–10
shows the fast
5–52. The
through
5–23
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