EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 483

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
July 2005
Table 5–2
and the selected serialization factor J (described in pervious sections). The
Quartus II software automatically generates the data input to the
additional transmitter data channel.
Center-Aligned Transmitter Clock Output
A negative-edge-triggered D flipflop (DFF) register is located between
the serial register of each data channel and its output buffer, as show in
Figure
center-aligned data is required. For center alignment, the DFF only shifts
the output from the channel used as the transmitter clock out. The
transmitter data channels bypass the negative-edge DFF. When you use
the DFF register, the data is transmitted at the negative edge of the
multiplied clock. This delays the transmitted clock output relative to the
data channels by half the multiplied clock cycle. This is used for
HyperTransport technology, but can also be used for any interface
requiring center alignment.
Note to
(1)
Table 5–2. Differential Transmitter Output Clock Division
This value is usually referred to as B.
5–7. The negative-edge-triggered DFF register is used when
10
10
Table
J
4
4
8
8
8
shows the divided-down version of the high-frequency clock
5–2:
High-Speed Differential I/O Interfaces in Stratix Devices
1010101010
1110000011
10101010
00110011
11000011
Data Input
1010
0011
Stratix Device Handbook, Volume 2
Output Clock Divided By
10
2
4
2
4
8
2
5–11
(1)