EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 342
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Fast PLLs
Figure 1–17. Stratix & Stratix GX Fast PLL Block Diagram
Notes to
(1)
(2)
(3)
1–32
Stratix Device Handbook, Volume 2
Global or
regional clock (1)
Clock
Input
The global or regional clock input can be driven by an output from another PLL or any dedicated CLK or FCLK pin.
It cannot be driven by internally-generated global signals.
In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix and Stratix GX
devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a high-speed differential I/O support SERDES control signal.
Figure
1–17:
Frequency
Detector
general purpose abilities of the Fast PLL. For information on the high-
speed differential I/O interface capabilities, see the High-Speed Differential
I/O Interfaces in Stratix Devices chapter.
Phase
PFD
Charge
Pump
Loop
Filter
VCO Phase Selection
Selectable at each PLL
Output Port
÷m
VCO
8
Post-Scale
Counters
÷g0
÷l0
÷l1
Altera Corporation
diffioclk1 (2)
Global or
regional clock
txload_en (3)
rxload_en (3)
Global or
regional clock
diffioclk2 (2)
Global or
regional clock
July 2005
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