EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 695

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
July 2005
Figure 10–5. Rising Edge Feed-Through Behavior
(Stratix & Stratix GX Devices)
Note to
(1)
Mixed-Port Read-During-Write Mode
Mixed-port read-during-write mode occurs when a RAM block in simple
or true dual-port mode has one port reading and the other port writing to
the same address location using the same clock. In APEX II and
APEX 20K designs, the ESB outputs the old data in the first half of the
clock cycle and the new data in the second half of the clock cycle, as
indicated by
Figure 10–6. Mixed-Port Feed-Through Behavior
(APEX II & APEX 20K Devices)
Note to
(1)
Stratix and Stratix GX device RAM outputs the new data on the rising
edge of the clock cycle immediately after the data was written. When you
use Stratix and Stratix GX M512 and M4K blocks, you can choose whether
to output the old data at the targeted address or output a don’t care value
during the clock cycle when the new data is written. M-RAM blocks
Figures 10–4
the outputs are not registered.
Figure 10–6
Figure
Figure
Figure
10–5:
10–6:
assumes that outputs are not registered.
and
Transitioning APEX Designs to Stratix & Stratix GX Devices
data_out
data_out
data_in
data_in
inclock
inclock
Port A
Port A
Port B
Port B
10–5
wren
wren
wren
10–6.
assume that the address stays constant throughout and that
Old
Old
Note (1)
Note (1)
A
A
A
A
Stratix Device Handbook, Volume 2
B
B
B
10–11