EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 296

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Contents
Section II. Memory
Chapter 2. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Chapter 3. External Memory Interfaces in Stratix & Stratix GX Devices
iv
Conclusion ............................................................................................................................................ 1–56
Revision History ..................................................................................................................... Section II–1
Introduction ............................................................................................................................................ 2–1
TriMatrix Memory ................................................................................................................................. 2–1
Using TriMatrix Memory ..................................................................................................................... 2–7
Clock Modes ......................................................................................................................................... 2–16
Designing With TriMatrix Memory .................................................................................................. 2–23
Read-During-Write Operation at the Same Address ..................................................................... 2–25
Conclusion ............................................................................................................................................ 2–27
Introduction ............................................................................................................................................ 3–1
External Memory Standards ................................................................................................................ 3–1
DDR Memory Support Overview ..................................................................................................... 3–10
VCCG & GNDG .............................................................................................................................. 1–52
External Clock Output Power ...................................................................................................... 1–53
Guidelines ........................................................................................................................................ 1–56
Clear Signals ...................................................................................................................................... 2–3
Parity Bit Support ............................................................................................................................. 2–3
Byte Enable Support ........................................................................................................................ 2–4
Implementing Single-Port Mode .................................................................................................... 2–7
Implementing Simple Dual-Port Mode ......................................................................................... 2–8
Implementing True Dual-Port Mode .......................................................................................... 2–11
Implementing Shift-Register Mode ............................................................................................. 2–14
Implementing ROM Mode ............................................................................................................ 2–15
Implementing FIFO Buffers .......................................................................................................... 2–16
Independent Clock Mode .............................................................................................................. 2–16
Input/Output Clock Mode ........................................................................................................... 2–18
Read/Write Clock Mode ............................................................................................................... 2–21
Single-Port Mode ............................................................................................................................ 2–23
Selecting TriMatrix Memory Blocks ............................................................................................ 2–24
Pipeline & Flow-Through Modes ................................................................................................ 2–24
Power-up Conditions & Memory Initialization ......................................................................... 2–25
Same-Port Read-During-Write Mode .......................................................................................... 2–25
Mixed-Port Read-During-Write Mode ........................................................................................ 2–26
DDR SDRAM .................................................................................................................................... 3–1
RLDRAM II ....................................................................................................................................... 3–4
QDR & QDRII SRAM ...................................................................................................................... 3–6
ZBT SRAM ......................................................................................................................................... 3–8
DDR Memory Interface Pins ......................................................................................................... 3–11
DQS Phase-Shift Circuitry ............................................................................................................ 3–15
Stratix Device Handbook, Volume 2
Altera Corporation