EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 860
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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1.5-V Regulator Application Examples
14–20
Stratix Device Handbook, Volume 2
Output voltage requirements
Supply voltages
Supply variance from Linear Technology data sheet
Estimated I
Estimated I
Total user-mode current consumption
Table 14–8. Voltage Regulator Selection Process for EP1C12F324C Design (Part 1 of 2)
Use Cyclone Power Calculator
Use Cyclone Power Calculator (not applicable in this example
because V
I
C C
= I
C C I N T
C C I N T
C C I O
C C I O
+ I
if regulator powers V
C C I O
= 3.3 V)
Synchronous Switching Regulator Example
This example shows a worst-case scenario for power consumption where
the design uses all the LEs and RAM.
requirements for 1.5-V design using a Cyclone EP1C12 FPGA.
Table 14–8
voltage regulator.
Output voltage precision requirement
Supply voltages available on the board
Voltage supply output current available for this
section (I
Variance of board supply (V
f
Average tog
Average tog
Utilization
Output and bidirectional pins
V
V
Efficiency
MAX
Table 14–7. Design Requirements for the Example EP1C12F324C
CCIO
CCINT
supply level
supply level
C C I O
I N , D C ( M A X )
uses the checklist on
IO
LC
Design Requirement
)
IN
)
page 14–9
Table 14–7
Supply variance = ±5%
to help select the appropriate
V
IN
shows the design
OR V
3.3 V
2 A
150 MHz
12.5%
12.5%
100%
125
3.3 V
1.5 V
5%
5%
90%
I
CCINT
V
I
CCIO
OUT
I
C C
CC
Altera Corporation
= 1.5 V
= 3.3 V
= 620 mA
= N/A
= 620 mA
Value
January 2005
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