EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 487

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 5–11. SDR Clock-to-Data Relationship
Figure 5–12. SDR Receiver & Transmitter Circuit Connection
Altera Corporation
July 2005
inclock
data rate = 624 Mbps
SDR
624 MHz
rx_d[15]
rxclk
rx_d[0]
XX
Stratix SERDES SDR Receiver
LVDS PLL
Channel
Channel
input clock × W
15
0
Serial-to-Parallel
Serial-to-Parallel
Register
Register
B0
automatically assigns a seventeenth channel as the transmitter clock
output. You can edge- or center-align the transmitter clock output by
selecting the default PLL phase or selecting the 90° phase of the PLL
output. On the receiver side, the clock signal is connected to the receiver
PLL's clock input, and you can assign identical clock-to-data alignment.
The multiplication factor W is calculated automatically. The data rate is
dividing by the input clock frequency to calculate the W factor. The
deserialization factor J may be 4, 7, 8, or 10.
Figure 5–11
center aligned with respect to data.
between the receiver and transmitter circuits.
rxloaden
Register
Register
Parallel
Parallel
shows an SDR clock-to-data timing relationship, with clock
8
8
High-Speed Differential I/O Interfaces in Stratix Devices
Stratix
Logic
Array
B1
LVDS PLL
8
8
txloaden
Stratix SERDES SDR Transmitter
Register
Register
Parallel
Parallel
Figure 5–12
input clock × W
Stratix Device Handbook, Volume 2
Parallel-to-Serial
Parallel-to-Serial
Register
Register
shows the connection
B2
Channel
Channel
Channel
15
16
0
data rate = 624 Mbps
624 MHz
624 MHz
txclk_out
txclk_in
tx_d[15]
tx_d[0]
B3
5–15