EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 440

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Stratix & Stratix GX I/O Standards
Figure 4–13. Differential SSTL-2 Class II Termination
4–12
Stratix Device Handbook, Volume 2
Transmitter
Differential
25 Ω
25 Ω
50 Ω
standard and supplements the SSTL-2 standard for differential clocks.
The differential SSTL-2 standard specifies an input voltage range of
– 0.3 V V
require an input reference voltage differential. See
on differential SSTL-2 termination. Stratix and Stratix GX devices support
output clock levels for differential SSTL-2 Class II operation. The output
clock is implemented using two single-ended output buffers which are
programmed to have opposite polarity.
LVDS - ANSI/TIA/EIA Standard ANSI/TIA/EIA-644
The LVDS I/O standard is a differential high-speed, low-voltage swing,
low-power, general-purpose I/O interface standard requiring a 3.3-V
V
data transfer, backplane drivers, and clock distribution. The
ANSI/TIA/EIA-644 standard specifies LVDS transmitters and receivers
capable of operating at recommended maximum data signaling rates of
655 Mbps. However, devices can operate at slower speeds if needed, and
there is a theoretical maximum of 1.923 Gbps. Stratix and Stratix GX
devices meet the ANSI/TIA/EIA-644 standard.
Due to the low voltage swing of the LVDS I/O standard, the
electromagnetic interference (EMI) effects are much smaller than CMOS,
TTL, and PECL. This low EMI makes LVDS ideal for applications with
low EMI requirements or noise immunity requirements. The LVDS
standard does not require an input reference voltage, however, it does
require a 100
buffer. Stratix and Stratix GX devices include an optional differential
LVDS termination resistor within the device using differential on-chip
termination. Stratix and Stratix GX devices support both input and
output levels.
V
CCIO
TT
= 1.25 V
. This standard is used in applications requiring high-bandwidth
I
50 Ω
V
V
TT
CCIO
termination resistor between the two signals at the input
= 1.25 V
+ 0.3 V. The differential SSTL-2 standard does not
Z
Z
0
0
= 50 Ω
= 50 Ω
50 Ω
V
TT
= 1.25 V
50 Ω
V
TT
= 1.25 V
Figure 4–13
Altera Corporation
Differential
Receiver
for details
June 2006