EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 463

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
June 2006
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As a result, the Quartus II Fitter does not count the bidirectional pin
potential outputs, and the number of V
legal range.
Toggle Rate Logic Option in Quartus II
You should specify the pin’s output toggling rate in order to perform a
stricter pad placement check in the Quartus II software. Specify the
frequency at which a pin toggles in the Quartus II Assignment Editor.
This option is useful for adjusting the pin toggle rate in order to place
them closer to differential pins. The option directs the Quartus II Fitter
toggle-rate checking while allowing you to place a single-ended pin
closer to a differential pin.
DC Guidelines
Variables affecting the DC current draw include package type and desired
termination methods. This section provides information on each of these
variables and also shows how to calculate the DC current for pin
placement.
1
For any 10 consecutive output pads in an I/O bank, Altera recommends
a maximum current of 200 mA for thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up packages and 164 mA for
non-thermally enhanced cavity up and non-thermally enhanced FineLine
BGA packages. The following equation shows the current density
limitation equation for thermally enhanced FineLine BGA and thermally
enhanced BGA cavity up packages:
The following equation shows the current density limitation equation for
non-thermally enhanced cavity up and non-thermally enhanced
FineLine BGA packages:
dm : OUTPUT_ENABLE_GROUP 1;
pin + 9
Σ
pin
The Quartus II software automatically takes these variables into
account during compilation.
I
pin
< 200 mA
Selectable I/O Standards in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
REF
bank outputs remains in the
4–35