EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 652

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Interfaces
Figure 8–6. Stratix & Stratix GX Device XSBI Transmitter Implementation
8–8
Stratix Device Handbook, Volume 2
Stratix & Stratix GX
PCS Transmitter
Stratix & Stratix GX
Logic Array
Fast PLL
4 or 8
4 or 8
The transmit serializer/deserializer (SERDES) clock comes from the
transmitter clock source (PMA_TXCLK_SRC). The receiver SERDES clock
comes from the PMA receiver recovered clock (PMA_RXCLK).
Figure 8–6
transmitted from the PCS to the PMA starts at the core of the Stratix or
Stratix GX device and travels to the Stratix or Stratix GX transmitter
SERDES block. The transmitter SERDES block converts the parallel data
to serial data for 16 individual channels (TX_D[15..0]). The PMA
source clock (PMA_TXCLK_SRC) is used to clock out the signal data.
PMA_TXCLK is generated from the same phase-locked loop (PLL) as the
data, and it travels to the PMA at the same rate as the data. By using one
of the data channels in the middle of the bus as the clock (in this case, the
eighth channel CH8), the clock-to-data skew improves.
Figure 8–7
side, data (RX_D[15..0]) comes from the PMA to the Stratix or
Stratix GX receiver SERDES block along with the PMA receiver clock
(PMA_RXCLK). The PMA receiver clock is used to convert the serial data
to parallel data. The phase shift or inversion on the PMA receiver clock is
needed to capture the receiver data.
Stratix & Stratix GX SERDES
÷J
Register
Parallel
622 MHz
× W
shows the transmitter output of the XSBI core. Data
shows the receiver input of the XSBI core. From the receiver
Parallel-to-Serial
Register
W = 1
CH16
J = 4 or 8
CH0
CH7
CH8
CH9
PMA_TXCLK_SRC
PMA_TXCLK
622 Mbps
TX_D[15]
622 MHz
TX_D[0]
TX_D[7]
TX_D[8]
Altera Corporation
Transmitter
PMA
July 2005