EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 747

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 11–15. Timing Waveform for Configuring Devices in FPP Mode
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
July 2005
t
t
t
t
t
t
t
CF2CK
DSU
DH
CFG
CH
CL
CLK
Table 11–9. FPP Timing Parameters for Stratix & Stratix GX Devices (Part 1 of 2)
Symbol
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
DCLK should not be left floating after configuration. It should be driven high or low, whichever is convenient.
DATA[] is available as user I/Os after configuration and the state of these pins depends on the dual-purpose pin
settings.
CONF_DONE (3)
Figure
nSTATUS (2)
nCONFIG
Data setup time before rising edge on
Data hold time after rising edge on
nCONFIG
DCLK
DCLK
DCLK
INIT_DONE
DATA[7..0}
nCONFIG
11–15:
User I/O
DCLK
high time
low time
period
high to first rising edge on
low pulse width
t
t
CF2CD
CFG
FPP Configuration Timing
Figure 11–15
Stratix GX device in FPP mode.
parameters for Stratix or Stratix GX devices.
t
CF2ST1
t
CF2ST0
t
CF2CK
t
ST2CK
Parameter
t
Byte 0 Byte 1 Byte 2 Byte 3
STATUS
High-Z
t
CH
t
CLK
t
DSU
t
CL
t
DH
shows FPP timing waveforms for configuring a Stratix or
DCLK
DCLK
DCLK
Table 11–9
Byte n
Configuring Stratix & Stratix GX Devices
Note (1)
Stratix Device Handbook, Volume 2
Min
40
40
10
7
0
4
4
shows the FPP timing
t
CD2UM
Max
User Mode
User Mode
(4)
(4)
Units
µs
ns
ns
µs
ns
ns
ns
11–29