EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 292

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

O
Ordering Information
Output Registers
Output Selection Multiplexer
P
Packaging
PCI-X 1.0 Specifications
Phase Shifting
PLL
Index–6
Parity Bit Support
Shift Register
Simple Dual-Port & Single-Port Memory
Stratix
Stratix
TriMatrix Memory
True
Device Pin-Outs
Packaging Ordering Information
Reference & Ordering Information
BGA Package Sizes
Device Speed Grades
FineLine BGA Package Sizes
Advanced Clear & Enable Control
Dynamically Programmable Counters & De-
Enhanced
Fast PLL
Row
Memory Configuration
Support
Fast PLLs
Channel Layout EP1S10, EP1S20 or
Channel
Configurations
Configuration
Configuration
Configuration
lays
PLLs
Mode
Signals
EP1S25 Devices
Devices
IOE
IOE
2–100
&
in
2–25
2–91
2–103
Layout
2–81
Dual-Port
2–64
Column
in
Stratix
2–36
in
2–43
5–1
2–139
2–24
2–21
5–1
1–4
DDR
2–112
2–114
2–22
4–10
2–23
DDR
1–5
EP1S30
Device
2–138
Interface
2–64
2–26
Output
1–5
Input
to
5–2
Enhanced
2–98
Memory
5–1
EP1S80
Unit
I/O
I/O
T
Testing
Timing
TriMatrix Memory
I/O Standards Supported for Enhanced PLL
Lock
PLL Locations
Programmable Bandwidth
Programmable Delay Chain
Programmable Duty Cycle
Reconfiguration
Temperature Sensing Diode
Temperature vs. Temperature-Sensing Diode
DSP
Dual-Port RAM Timing Microparameter
External Timing in Stratix Devices
High-Speed I/O Timing
High-Speed
Internal Parameters
IOE
LE Internal Timing Microparameters
Logic Elements Internal Timing Microparam-
Model
PLL Timing
Preliminary & Final
Stratix Device Timing Model Status
Stratix JTAG
TriMatrix Memory Features
Port I/O Standards
Electrical Characteristics
External
Block Internal Timing
Timing Parameters & Values
Pins
Locked
Voltage
Waveform
Terminology
Descriptions
eter Descriptions
Internal
Detect
4–19
Microparameter
Microparameters
Stratix Device Handbook, Volume 1
2–94
3–14
4–94
Timing
2–98
3–15
2–84
&
2–90
Timing
4–27
Descriptions
4–22
4–87
Programmable
4–22
4–19
2–102
4–22
Specifications
4–87
Altera Corporation
2–91
2–98
Microparameter
3–14
4–29
2–111
2–21
3–13
3–4
4–23
4–33
4–19
4–28
Gated
&