EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 339
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Figure 1–16. VCO Frequency Modulation Waveforms
Altera Corporation
July 2005
VCO Frequency
count2 values
count1 values
f
Software Support
You can enter the desired down-spread percentage and modulation
frequency in the MegaWizard Plug-In Manager through the Quartus II
software. Alternatively, the MegaWizard Plug-In Manager can set the
downspread parameter in the altpll megafunction to the desired
down-spread percentage. Timing analysis ensures the design operates at
the maximum spread frequency and meets all timing requirements.
For more information on PLL software support in the Quartus II
software, see the altpll Megafunction User Guide.
Guidelines
If the design cascades PLLs, the source, or upstream PLL should have a
low bandwidth setting, while the destination, or downstream PLL should
have a high bandwidth setting. The upstream PLL must have a low
bandwidth setting because a PLL does not generate jitter higher than its
bandwidth. The downstream PLL must have a high bandwidth setting to
track the jitter. The design must use the spread-spectrum feature in a low-
bandwidth PLL and, therefore, the Quartus II software automatically sets
the spread-spectrum PLL’s bandwidth to low.
1
Stratix and Stratix GX devices can accept a spread-spectrum input with
typical modulation frequencies. However, the device cannot
automatically detect that the input is a spread-spectrum signal. Instead,
the input signal looks like deterministic jitter at the input of the
downstream PLL.
Spread spectrum should only have a minor effect on period jitter, but
period jitter increases. Period jitter is the deviation of a clock’s cycle time
from its previous cycle position. Period jitter measures the variation of a
clock’s output transition from its ideal position over consecutive edges.
Designs cannot use spread-spectrum PLLs with the
programmable bandwidth feature.
General-Purpose PLLs in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
1–29
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