EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 341

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Fast PLLs
Altera Corporation
July 2005
PLL5_OUT[3..0]p/n
PLL6_OUT[3..0]p/n
PLL11_OUT, CLK13n
PLL12_OUT, CLK6n
VCCA_PLL5
VCCG_PLL5
GNDA_PLL5
GNDG_PLL5
VCCA_PLL6
VCCG_PLL6
GNDA_PLL6
GNDG_PLL6
VCCA_PLL11
VCCG_PLL11
GNDA_PLL11
GNDG_PLL11
VCCA_PLL12
VCCG_PLL12
GNDA_PLL12
GNDG_PLL12
VCC_PLL5_OUTA
VCC_PLL5_OUTB
VCC_PLL6_OUTA
VCC_PLL6_OUTB
Table 1–9. Enhanced PLL Pins (Part 2 of 2)
Pin
Single-ended or differential pins driven by extclk[3..0] ports from PLL 5.
Single-ended or differential pins driven by extclk[3..0] ports from PLL 6.
Single-ended output pin driven by clk0 port from PLL 11.
Single-ended output pin driven by clk0 port from PLL 12.
Analog power for PLL 5. Connect this pin to 1.5 V, even if the PLL is not used.
Guard ring power for PLL 5. Connect this pin to 1.5 V, even if the PLL is not used.
Analog ground for PLL 5. You can connect this pin to the GND plane on the board.
Guard ring ground for PLL 5. You can connect this pin to the GND plane on the board.
Analog power for PLL 6. Connect this pin to 1.5 V, even if the PLL is not used.
Guard ring power for PLL 6. Connect this pin to 1.5 V, even if the PLL is not used.
Analog ground for PLL 6. You can connect this pin to the GND plane on the board.
Guard ring ground for PLL 6. You can connect this pin to the GND plane on the board.
Analog power for PLL 11. Connect this pin to 1.5 V, even if the PLL is not used.
Guard ring power for PLL 11. Connect this pin to 1.5 V, even if the PLL is not used.
Analog ground for PLL 11. You can connect this pin to the GND plane on the board.
Guard ring ground for PLL 11.You can connect this pin to the GND plane on the board.
Analog power for PLL 12. Connect this pin to 1.5 V, even if the PLL is not used.
Guard ring power for PLL 12. Connect this pin to 1.5 V, even if the PLL is not used.
Analog ground for PLL 12. You can connect this pin to the GND plane on the board.
Guard ring ground for PLL 12. You can connect this pin to the GND plane on the board.
External clock output V
and PLL5_OUT1n outputs from PLL 5.
External clock output V
and PLL5_OUT3n outputs from PLL 5.
External clock output V
and PLL5_OUT1n outputs from PLL 6.
External clock output V
and PLL5_OUT3n outputs from PLL 6.
Stratix devices contain up to eight fast PLLs and Stratix GX devices
contain up to four fast PLLs. Both device PLLs have high-speed
differential I/O interface ability along with general-purpose features.
Figure 1–17
shows a diagram of the fast PLL. This section discusses the
CCIO
CCIO
CCIO
CCIO
General-Purpose PLLs in Stratix & Stratix GX Devices
power for PLL5_OUT0p, PLL5_OUT0n, PLL5_OUT1p,
power for PLL5_OUT2p, PLL5_OUT2n, PLL5_OUT3p,
power for PLL5_OUT0p, PLL5_OUT0n, PLL5_OUT1p,
power for PLL5_OUT2p, PLL5_OUT2n, PLL5_OUT3p,
Description
Stratix Device Handbook, Volume 2
1–31