EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 636

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Discrete Cosine Transform (DCT)
7–58
Stratix Device Handbook, Volume 2
Figure 7–36. Details on the Implementation of the Multiply-Addition Operation
in Stage 4 of the 1-D DCT Algorithm
Note to
(1)
DCT Implementation Results
Table 7–18
precision, as shown in
DCT Design Example
Download the 2-D convolutional filter (d_dct.zip) design example from
the Design Examples section of the Altera web site at www.altera.com.
Part
Utilization
Performance
Latency
Table 7–18. 2-D DCT Implementation Results
Referring to
matrix coefficient. C
Figure
DSP Block - Four-Multipliers Adder Mode (18-bit)
C
S3
C
S3
C
S3
C
S3
shows the results of implementing a 2-D DCT with 18-bit
m4
m2
m3
m1
2
3
4
1
7–36:
Figure
7–33. S3
x
EP1S20F780
Lcell: 1717/18460 (9%)
DSP Block 9-bit element: 18/80 (22%)
Memory bits: 2816/1669248 (<1%)
165 MHz
80 clock cycles
= cos (x /16).
Figure
n
is an output from stage 3 of the DCT and C
7–35.
Altera Corporation
September 2004
y
k
mn
is a